The present invention relates to a semiconductor non-volatile memory cell, a method of producing the semiconductor non-volatile memory cell, a semiconductor non-volatile memory having the semiconductor non-volatile memory cell, and a method of producing the semiconductor non-volatile memory.
Conventionally, a semiconductor non-volatile memory cell is an element of a semiconductor non-volatile memory. The semiconductor non-volatile memory cell is categorized in two types, i.e., a semiconductor non-volatile memory cell having a planer structure and a semiconductor non-volatile memory having a three-dimensional structure.
Patent Reference 1 has disclosed a conventional semiconductor non-volatile memory cell 1000 having a planer structure. FIG. 12 is a schematic sectional view showing the conventional semiconductor non-volatile memory cell having the planer structure. As shown in FIG. 12, an electric charge accumulation portion formed of a laminated insulation layer is disposed on a sidewall portion of a gate electrode of an NMOSFET (N-type Metal Oxide Semiconductor Field Effect Transistor).
Patent Reference 1: Japanese Patent Publication No. 2006-24680
In the conventional semiconductor non-volatile memory cell 1000 having the planer structure, a drain region 1021 of an n+ type and a source region 1022 of the n+ type are separately formed in a p-well 1011 formed on a p-type silicon substrate 1010. A channel forming region 1012 is disposed between the drain region 1021 and the source region 1022.
A gate insulation film 1013 is formed on the channel forming region 1012, and a gate electrode 1030 is formed on the gate insulation film 1013. A first resistivity changing portion 1023 is disposed between the drain region 1021 and the channel forming region 1012. A first electric charge accumulation portion 1050 is formed on the first resistivity changing portion 1023. The first electric charge accumulation portion 1050 is formed of a silicon oxide film 1042, a silicon nitride film 1042, and a silicon oxide film 1043.
A second resistivity changing portion 1026 is disposed between the source region 1022 and the channel forming region 1012. A second electric charge accumulation portion 1052 is formed on the second resistivity changing portion 1026. The second electric charge accumulation portion 1052 is formed of a silicon oxide film 1044, a silicon nitride film 1045, and a silicon oxide film 1046.
When the conventional semiconductor non-volatile memory cell 1000 having the planer structure is operated, hot carriers are introduced into the first electric charge accumulation portion 1050 or the second electric charge accumulation portion 1052, thereby recording electric charges thus accumulated as information. More specifically, a state that the electric charges are accumulated, or a state that the electric charges are not accumulated, corresponds to a logic value “0” or “1”, thereby making it possible to record one bit information.
It is possible to determine whether the electric charges are accumulated in the first electric charge accumulation portion 1050 through the following phenomena. When the electric charges are accumulated in the first electric charge accumulation portion 1050, a resistivity of the first resistivity changing portion 1023 increases. Accordingly, an electric current flowing between the source region 1022 and the drain region 1021 decreases.
On the other hand, when the electric charges are not accumulated in the first electric charge accumulation portion 1050, a resistivity of the first resistivity changing portion 1023 decreases. Accordingly, a sufficient amount of an electric current flows between the source region 1022 and the drain region 1021.
When the electric charges are accumulated, a positive voltage is applied to the source region 1022 and the drain region 1021, and the source region 1022 is set to be ground voltage. In the above description, information is recorded in the first electric charge accumulation portion 1050, and information may be recorded in the first electric charge accumulation portion 1050 through a similar process.
Patent Reference 2 or 3 has disclosed a semiconductor non-volatile memory cell having a fin-type transistor 2000 as an example of a conventional semiconductor non-volatile memory cell having a three-dimensional structure. FIG. 13 is a schematic perspective view showing the fin-type transistor 2000.
Patent Reference 2: Japanese Patent Publication No. 2004-88101
Patent Reference 3: Japanese Patent Publication No. 2004-128185
As shown in FIG. 13, the conventional semiconductor non-volatile memory cell is characterized in that a gate electrode is formed to cover a top portion and a side portion of an Si (Silicon) substrate or an SOI (Silicon On Insulator) substrate having a fin shape protruding in a vertical direction.
More specifically, in the fin-type transistor 2000, an SOI substrate is formed of a silicon substrate 2010, an embedded silicon oxide film 2011, and an SOI layer as an uppermost layer. The SOI layer is processed to form a silicon fin 2012 on the embedded silicon oxide film 2011. A gate oxide film 2013 is formed on surfaces of the embedded silicon oxide film 2011 and the silicon fin 2012.
The silicon fin 2012 has a size according to a generation of device development, and has typically a width of about 15 nm and a height of about 50 nm. A gate electrode 2014 is disposed to cover a part of the silicon fin 2012 with the gate oxide film 2013 formed thereon.
Further, a source region (not shown in FIG. 13) and a drain region 2016 are formed on portions of the silicon fin 2012 where the gate oxide film 2013 is removed, so that the source region and the drain region 2016 sandwich the gate electrode 2014 at a middle portion in a longitudinal direction of the silicon fin 2012. Note that, in the conventional semiconductor non-volatile memory cell having the three-dimensional structure, a portion corresponding to the electric charge accumulation layer of the conventional semiconductor non-volatile memory cell having the planer structure is disposed at a position other than the transistor portion, thereby not being shown in FIG. 13.
With the configuration described above, a channel width of the transistor is determined by the side surface and the top surface of the fin, and becomes substantially longer than a width of the top surface of the fin, i.e., a layout width. Accordingly, as opposed to the transistor having the planer structure, the fin-type transistor has an increased current drive power. As a result, it is possible to alleviate a problem of decrease in a current value of the transistor due to a decrease in a channel width of the conventional semiconductor non-volatile memory cell having the planer structure.
When a memory cell region having a memory element and a peripheral region having a peripheral element are integrated to from a semiconductor memory, it is difficult to uniformly flatten in a flattening process due to a difference in trench pattern densities between the memory cell region and the peripheral region. To solve the problem, Patent Reference 4 or 5 has proposed a method, in which a dummy trench pattern or a dummy active is formed in an intermediate region, where no insulation separation is necessary, between the memory cell region and the peripheral region, thereby performing the flattening process uniformly.
Patent Reference 4: Japanese Patent Publication No. 03-82053
Patent Reference 5: Japanese Patent Publication No. 2007-49119
Recently, with an advancement of a scaling such as a reduction in a size of a gate electrode through reducing a size of an element, the conventional semiconductor non-volatile memory cell having the planer structure tends to have a short channel effect due to a reduction in a gate electrode length or a gate electrode width.
In order to reduce the short channel effect, it is necessary to increase an impurity concentration of the channel. As a result, a mobility of carriers tends to decrease, or a current value of the transistor tends to decrease, thereby deteriorating a characteristic or function of the conventional semiconductor non-volatile memory cell.
In the fin-type transistor, it is possible to utilize the both sides of the fin, and to prevent the problem of the reduction in a current value of the transistor due to the reduction in the channel width, which occurs in the conventional semiconductor non-volatile memory cell having the planer structure. However, it is necessary to provide the electric charge accumulation portion at a position other than the transistor portion.
Further, when the fin-type transistor with a good transistor characteristic is mounted as the conventional semiconductor non-volatile memory cell together with a peripheral element to form the conventional semiconductor non-volatile memory cell, it is possible to solve the problems of the insulation separation or the flattening process described above through a well-known STI (Shallow Trench Isolation) method, a CMP (Chemical Mechanical Polishing) method, or an etch-back method.
In this case, however, when a film covering the memory cell is patterned, a portion of the film thus etched may adhere again to a step portion, in particular, a lower step portion at an edge portion of the memory cell adjacent to the peripheral element, thereby causing a short circuit at the step portion. Accordingly, a yield or reliability of the conventional semiconductor non-volatile memory cell is deteriorated.
In view of the problems described above, an object of the present invention is to provide a semiconductor non-volatile memory cell and a method of producing the semiconductor non-volatile memory cell capable of solving the problems of the conventional semiconductor non-volatile memory cell. In the semiconductor non-volatile memory cell, it is possible to provide an electric charge accumulation portion, and to obtain high current efficiency.
Further, another object of the present invention is to provide a semiconductor non-volatile memory and a method of producing the semiconductor non-volatile memory with a high yield and improved reliability, in which it is possible to easily integrate the semiconductor non-volatile memory cell and a peripheral element.
Further objects and advantages of the invention will be apparent from the following description of the invention.